1. Technical Field of the Invention
The invention relates generally to communication systems; and, more particularly, it relates to decoding processing within such communication systems.
2. Description of Related Art
Various communication systems have been under constant development for many years. Within certain types of communication systems, FEC (Forward Error Correction) is employed such that various parameters employed within the receiver end/decoder end of a communication channel are appropriately suited to be able to correct for most (ideally, any) errors that may be introduced within signal transmitted across the communication channel from a transmitter end to a receiver end. Sometimes, it is desirable to adjust certain of the various operational parameters within a receiver end communication device in an effort to compensate for any changes to the operating conditions (or communication device status) thereby providing relatively good performance and error correction.
However, in order to change these operational parameters within an FEC functional block within a receiver end communication device, the parameter configuration should be changed on the fly (i.e., in real time) for adaptive modulation and coding. In order to support this approach to performing FEC decoding, the FEC decoding parameters must be known and programmed to an FEC decoding functional block before input signals get into the FEC block. However, the approaches for doing this within the prior art do not provide for very operation and performance.
One prior art way of adaptively modifying the operational parameters for an FEC block is to send the FEC parameter information in frame headers and to extract the FEC parameters out of them. Once these FEC decoding parameters have been extracted from the frame headers, then those FEC decoding parameters may then be programmed back to the corresponding FEC block. This approach is typically a 1 to 1 approach, in that, a header includes FEC operational parameter information corresponding to an immediately following and subsequent FEC block. This prior art is shown pictorially in the following described prior art figures.
FIG. 1A is a diagram illustrating an embodiment of a prior art frame structure. In this illustration, it can be seen that the frame header immediately preceding an FEC block includes the FEC operational parameters that correspond to the immediately following FEC block. This information immediately extracted from the header is then employed to configure the FEC decoding parameters that are used to perform the FEC decoding of the FEC block immediately following the frame header. This prior art inherently involves an undesirable decoding and operational latency, in that, the header of the FEC block must be processed (to extract the information corresponding to the FEC operational parameters by which the subsequent FEC block is to be decoded), then the FEC block must be configured according to that extracted information, and then the FEC block is then actually decoded. This latency is existent for each and every header and FEC block combination within this prior art approach.
FIG. 1B is a diagram illustrating an embodiment of a prior art receiver architecture that may be employed to effectuate the approach of the corresponding FIG. 1A described above. An input signal is first provided to a demodulator that performs any of the necessary demodulation of the received signal to get it into a format that is appropriate for subsequent FEC decoding. In addition, the output of the demodulator is simultaneously provided to a parameter extraction functional block and to a FEC decoding functional block. The FEC decoding functional block must wait for the extraction of the FEC decoding parameters from the parameter extraction functional block before performing FEC decoding in a manner that is appropriate for the FEC block that immediately follows the frame header from which the FEC decoding parameters have been extracted. Again, it can be seen that this latency with respect to this prior art approach to adjust the FEC operational parameters involves processing the header that includes information corresponding to the FEC operational parameters, configuring the FEC functional block according to the most recently extracted FEC operational parameters, and then performing the actually decoding using the FEC decoding functional block of the corresponding FEC block for which these FEC operational parameters correspond.
Moreover, in this prior art approach, the frame headers are either not protected by any error control code, or they are protected by a different FEC that protects the FEC blocks within the input signal stream. This different FEC that may be employed to protect the frame headers is less powerful than the one for the actual data part of the input signal stream. This type of prior art receiver suffers from many deficiencies.
For example, it cannot operate at low SNR (Signal to Noise Ratio) because the frame headers are vulnerable to noise, as they are typically not protected by any error control code. Also, this prior art approach suffers from the inherently slow and serial approach performed by this prior art receiver architecture that includes a parameter extraction functional block that must be employed before performing any FEC decoding of the FEC blocks of the input signal stream that immediately follow the frame header (e.g., the frame header that includes the FEC decoding parameters for that immediately following FEC block). Also in the prior art, the information pertaining to the FEC parameters is embedded in the header before the FEC, and it uses a different coding than the data part of the input signal stream or no coding at all thereby providing little protection.
As such, it is clear that there is a need in the art for a manner by which FEC operational parameters may be modified and adjusted on the fly (i.e., in real time) to effectuate higher performance within error correctional coding communication systems.